The present invention generally relates to non-volatile memory devices, and more particularly, to memory devices that use magnetic memory cells.
One type of non-volatile memory known in the art relies on magnetic memory cells. These devices, known as magnetic random access memory (MRAM) devices, include an array of magnetic memory cells. The magnetic memory cells may be of different types. For example, a magnetic tunnel junction (MTJ) memory cell or a giant magnetoresistive (GMR) memory cell.
Generally, the magnetic memory cell includes a layer of magnetic film in which the orientation of magnetization is alterable and a layer of magnetic film in which the orientation of magnetization may be fixed or xe2x80x9cpinnedxe2x80x9d in a particular direction The magnetic film having alterable magnetization is referred to as a sense layer or data storage layer and the magnetic film that is fixed is referred to as a reference layer or pinned layer. A barrier layer separates the sense layer and the reference layer.
Conductive traces referred to as word lines and bit lines are routed across the array of memory cells. Word lines extend along rows of the memory cells and bit lines extend along columns of the memory cells. A memory cell stores a bit of information as an orientation of magnetization in a sense layer at each intersection of a word line and a bit line. The orientation of magnetization in the sense layer aligns along an axis of the sense layer referred to as its easy axis. The orientation of magnetization does not easily change along an axis orthogonal to the easy axis, referred to as the hard axis. Magnetic fields are applied to flip the orientation of magnetization in the sense layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer.
Conductive traces referred to as write lines are routed across the array of memory cells to aid in flipping the orientation of magnetization in sense layers. Write lines extend along columns of memory cells near their reference layers and parallel to bit lines. Word lines, which extend along rows of the memory cells, are near the sense layers. A memory cell is situated at each intersection of a write line and a word line. The write lines and word lines are electrically coupled to a write circuit
During a write operation, the write circuit selects one word line and one write line to change the orientation of magnetization in the sense layer of the memory cell situated at the conductors crossing point. The write circuit supplies write currents to the selected word line and write line to create magnetic fields in the selected memory cell. These write currents may be the same or different in magnitude. The magnetic fields combine to switch the orientation of magnetization in the selected memory cell from parallel to anti-parallel or vice versa.
The resistance through a memory cell differs according to the parallel or anti-parallel orientation of magnetization of the sense layer and the reference layer. This resistance is highest when the orientation is anti-parallel, i.e., the logic (1) state, and lowest when the orientation is parallel, i.e., the logic (0) state. The resistive logic state of the memory cell can be determined by sensing the resistance of the memory cell.
Word lines and bit lines aid in sensing the resistance of a memory cell. Word lines, which extend along rows, are electrically coupled to sense layers and bit lines, which extend along columns, are electrically coupled to reference layers. Word lines and bit lines are also electrically coupled to a read circuit to determine the resistance and state of a memory cell.
During a read operation, the read circuit selects one word line and one bit line to determine the resistance of the memory cell situated at the conductors crossing point. The read circuit may supply a voltage across the selected memory cell to generate a current through the memory cell. The read circuit detects this sense current, which represents the resistance of the memory cell. In one configuration, this resistance is compared to a reference resistance to determine the state of the memory cell. The reference resistance is used to differentiate a high resistive state from a low resistive state, which can be a challenging task.
The resistance through a memory cell vanes from cell to cell in the same array and from memory device to memory device. This resistance is dependent on barrier layer thickness and memory cell area. The barrier layer is a very thin insulating layer between the sense layer and the reference layer. This insulating layer may be aluminum oxide only Angstroms thick. The resistance of a memory cell varies exponentially with the thickness of the barrier layer. A change in barrier layer thickness of only two percent may change the resistance through the memory cell by a factor of two. Even with tight controls the resistance through memory cells in one device may greatly vary from the resistance through memory cells in another device. For this reason, using one resistance value for all devices is not practical. To get around this, memory cells have been converted to use as reference cells. These reference cells are used to get a reference resistance for a particular array or set of memory cells. However, the resistance through memory cells in the same array varies from cell to cell due to barrier layer thickness changes. Also, the resistance through a memory cell is dependent on memory cell area, and memory cell lengths and widths in the same array vary from cell to cell due to photolithography limitations. For these reasons, one memory cell resistance converted to a reference cell resistance may not be adequate for differentiating a high resistive state from a low resistive state.
Embodiments of the present invention provide a magnetic memory. In one embodiment, the magnetic memory comprises a memory cell configured to provide a resistive state, and a reference cell. The reference cell is substantially larger than the memory cell and configured to provide a reference resistance for determining the resistive state of the memory cell.